Thin dice by thinning wafer after dicing

Thinner Dice, the Ultimate Step for Miniaturization

Chip scale packaging technology is advancing with thinner dice that can fit into thinner packages. Intel Corp. has licensed from Tessera Inc. a process for placing several dice into a 1-mm high multichip package. This is an example of the system-in-package technology.

We are wafer and die thinning and dicing specialists for all semiconductor materials including GaAs, InP, SiGe, GaSb, GaP and InSb, Silicon, Optical Glasses, Sapphire and many others. One of our processes consists of partially dicing the wafer to a predetermined depth, depending on the final thickness of the die, mounting with the diced surface down and then thinning leaving the surface rough, semi-polished or fully polished.

We have also perfected a process for thinning completely singulated dice. For example: a customer will submit 100 dice where length and width is 0.100" x 0.050" x 0.20" thick, with desired final thickness at 0.003" (75 microns) max. thickness. The final surface finish can be from rough to a fine polish with almost no edge drop-off.

Standard wafer thinning is available for fully patterned live product to thicknesses of less than 0.003" (75 microns) and diameters up to 12" (300mm).

Commercial applications for thinned semiconductor circuitry include:

  • Electro-optics devices
  • Substrate-less McM
  • Thin multi-chip modules
  • System-in-package
  • Smart card modules
  • Folded-dice packaging





Go to

Return to Home Page: Dicing hybrid, semiconductor and dicing MEMS wafers

print page




Valley Design East
Phoenix Park Business Center
2 Shaker Road, Bldg. E-001
Shirley, MA 01464
Phone: 978.425.3030
Fax: 978.425.3031
Valley Design
Santa Cruz, CA 95060  
Phone: 831.420.0595  
Fax: 831.420.0592

©2015 Valley Design Corp. All Rights Reserved